1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to a thyristor or Silicon Controlled Rectifier (SCR) device with a capacitive trigger.
2. Description of the Related Art
A thyristor, also known as a Silicon Controlled Rectifier (SCR), is a solid state latching device that can be used for a number of purposes. A thyristor has two stable states: a normal OFF state in which it presents a high impedance between its output terminals; and an ON state in which it presents a low impedance. The thyristor is triggered or switched from the OFF state to the ON state by the application of a suitable voltage signal, and remains in the ON state after the signal is removed.
A prior art thyristor 10 such as described in U.S. Pat. No. 5,225,702, entitled SILICON CONTROLLED RECTIFIER STRUCTURE FOR ELECTROSTATIC DISCHARGE PROTECTION, issued Jul. 6, 1993 to A. Chatterjee, is illustrated in FIGS. 1a and 1b. FIG. 1a is an equivalent electrical schematic diagram of the thyristor 10 as implemented using discrete transistors, and FIG. 1b is a diagram illustrating the thyristor 10 formed as an integral PNPN device.
As viewed in FIG. 1a, the thyristor 10 comprises two bipolar transistors, more specifically a PNP transistor 12 and an NPN transistor 14. The emitter of the transistor 12 is connected via a terminal 16 to a positive voltage source VDD, whereas the emitter of the transistor 14 is connected via a terminal 18 to a voltage source VSS which is negative relative to the voltage source VDD. The voltage source VSS can be constituted by a ground connection.
The base of the transistor 12 is connected to the collector of the transistor 14, and the base of the transistor 14 is connected to the collector of the transistor 12. The collector of the transistor 12 is connected to the terminal 18 through a resistor 20, whereas the collector of the transistor 14 is connected to the terminal 16 through a resistor 22. Although the resistors 20 and 22 can be replaced with direct wire connections, the resistors 20 and 22 are preferably included because they reduce the voltage required to trigger the thyristor 10.
The thyristor 10 implemented as a PNPN device is illustrated in FIG. 1b, comprising a first P-region 24, a first N-region 26, a second P-region 28 and a second N-region connected in series between the terminals 16 and 18. The emitter, base and collector of the transistor 12 are constituted by the regions 24, 26 and 28, and the collector, base and emitter of the transistor 14 are constituted by the regions 26, 28 and 30 respectively.
In one application of the thyristor 10, a trigger input terminal (not shown) is connected to the base of the transistor 14, and the thyristor 10 is triggered by a positive trigger signal applied to the input terminal.
More specifically, the transistor 12 is normally reverse biased by the positive voltage applied through the resistor 22 from the terminal 16, and the transistor 14 is normally reverse biased by the negative voltage applied through the resistor 20 from the terminal 18. Both transistors 12 and 14 are turned off, and the thyristor 10 presents a high impedance OFF state between the terminals 16 and 18.
A positive trigger signal applied to the base of the transistor 14 turns on the transistor 14, thereby connecting the base of the transistor 12 to the negative voltage at the terminal 18. This turns on the transistor 12, thereby connecting the base of the transistor 14 to the positive voltage at the terminal 16 and turning on the transistor 14. With both transistors 12 and 14 turned on, the thyristor 10 presents a low impedance ON state between the terminals 16 and 18.
Both transistors 12 and 14 will maintain each other turned on after the trigger signal is removed. The transistors 12 and 14 can be turned off to return the thyristor 10 to the OFF state by reducing the potential between the terminals 16 and 18 to below a certain level. The thyristor 10 can alternatively triggered by applying a negative trigger signal to the base of the transistor 12.
Another application for a thyristor to which the present application is specifically intended is in ElectroStatic Discharge (ESD) protection. In this case, a thyristor is provided across the input or output terminal or contact pad of an integrated circuit or other device to protect the internal circuitry from potential damage from inadvertently applied electrostatic voltages.
Human beings, for example personnel handling integrated circuits, can develop high electrostatic voltages on their fingers which can be applied to the terminals of the integrated circuits. These electrostatic voltages can be as high as several thousand volts, and can easily destroy microelectronic devices connected to the terminals. Metal-Oxide-Semiconductor (MOS) circuits are especially vulnerable to such damage.
For this reason, thyristors are provided across the terminals to dissipate electrostatic voltages and protect circuitry as described in the above referenced patent to Chatterjee. In such an application, no trigger input is provided, and the thyristor 10 is connected across the input and/or output terminals of the integrated circuit.
The thyristor 10 remains in the OFF state as long as the voltage across the terminals 16 and 18 is below a certain value. When this value is exceeded, avalanche breakdown occurs across the PN junctions between the regions 24,26 and the regions 28,30, thereby causing the transistors 12 and 14 to be turned on as described above. The thyristor 10 is switched to its 0N state, thereby providing a low impedance shunt across the circuitry connected to the terminal through which the electrostatic voltage can be safely discharged.
The trigger voltage of a thyristor used for ESD protection must be above the normal operating voltage range of the circuitry to prevent false triggering, and below the voltage at which damage to the circuitry will occur. This presents a problem in newer microelectronic integrated circuits which operate at reduced voltage levels. Conventional thyristors are triggered for avalanche breakdown at voltages of approximately 15 volts, which is too high to protect the newer low voltage devices.